1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming a replacement gate structure on a semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Typically, a high performance integrated circuit product, such as a high performance microprocessor, will contain billions of individual field effect transistors (FETs). The transistors are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region of the transistor. The transistor devices come in a variety of forms, e.g., so-called planar transistor devices, 3D or FinFET devices, etc.
FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E, i.e., in the source/drain regions of the device A, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes. In the FinFET device, the gate structure D may enclose both the sides and the upper surface of all or a portion of the fins C to form a tri-gate structure, i.e., a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer (not shown), e.g., silicon nitride, is positioned at the top of the fins C and the FinFET device only has a dual-gate structure (sidewalls only). Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. The gate structures D for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
For many early device technology generations, the gate structures of most transistor elements (planar and FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
As mentioned above, the replacement gate process may be used when forming planar devices or 3D devices. FIGS. 1B-1J are cross-sectional views taken through the long axis of a fin C (i.e., in the current transport direction) that simplistically and idealistically depict one illustrative prior art method for forming an HK/MG replacement gate structure using a replacement gate technique on a FinFET transistor device.
FIG. 1B depicts the device 10 after several operations were performed. More specifically, at the point of fabrication depicted in FIG. 1B, the basic fin structures C and isolation regions 13 were formed in the substrate. Also depicted is a sacrificial gate structure 40 comprised of a sacrificial gate insulation layer 14 and a dummy or sacrificial gate electrode 15. A gate cap layer 16 is positioned above the sacrificial gate electrode 15. The structure depicted in FIG. 1B may be formed by thermally growing the sacrificial silicon dioxide gate insulating layer 14 and then depositing a gate electrode material (e.g., polysilicon) layer and a gate cap material layer (e.g., silicon nitride) above the substrate. Thereafter, the gate electrode material layer and the gate cap layer are patterned by performing known photolithography and etching processes using the sacrificial gate insulation layer 14 as an etch stop layer. Although the exposed portions of the sacrificial gate insulation layer 14 are depicted as having survived the gate patterning process, in practice, at least some of the thickness of the sacrificial gate insulation layer 14 will be consumed in the process of patterning the sacrificial gate structure 40.
In forming a transistor device, various ion implantation processes are performed to introduce various dopant materials into the fin C to form source/drain regions for the device. Of course, the type of dopants implanted, either N-type or P-type dopants, depends upon the type of transistor being made, i.e., an NMOS transistor or a PMOS transistor, respectively. A typical implantation sequence would involve formation of so-called halo implant regions, source/drain extension implant regions and deep source/drain implant regions. For an NMOS device, the halo implant region would be formed with a P-type dopant, while the extension and deep source/drain implant regions would be formed using an N-type dopant material. Accordingly, FIG. 1C depicts the device 10 after an ion implantation process 18 was performed to form so-called extension implant regions 18A in the fin C. A halo implantation process would also be performed to form halo implant regions (not shown) in the fin C at this point in the process flow. Although the arrows representing the implantation process 18 are vertically oriented, the extension implantation process and the halo implant process may be performed at an angle relative to the vertical to insure placement to the implanted materials at the desired location. The masking layer(s) that would be used during the implantation sequence discussed herein are not depicted in the drawings.
FIG. 1D depicts the device 10 after sidewall spacers 20 were formed proximate the sacrificial gate structure 40.
FIG. 1E depicts the device 10 after a second ion implantation process 21 was performed on the transistor 10 to form so-called deep source/drain implant regions 21A in the fins C. The ion implantation process performed to form the deep source/drain implant regions 21A is typically performed using a higher dopant dose and it is performed at a higher implant energy than the ion implantation process that was performed to form the extension implant regions 18A.
Thereafter, as shown in FIG. 1F, a heating or anneal process is performed to form the final source/drain regions 22 for the transistor 10. This heating process repairs the damage to the lattice structure of the fin material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice.
FIG. 1G depicts the device 10 after several process operations were performed. First, a layer of insulating material 23 was deposited above the device 10. Thereafter, a chemical mechanical planarization process was performed to remove the gate cap layer 16 and expose the sacrificial gate electrode 15.
Next, as shown in FIG. 1H, one or more etching processes were performed to remove the sacrificial gate electrode 15 and the sacrificial gate insulation layer 14 to thereby define a replacement gate cavity 24 where a replacement gate structure will subsequently be formed. Typically, the sacrificial gate insulation layer 14 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 14 may not be removed in all applications. Even in cases where the sacrificial gate insulation layer 14 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the fin within the gate cavity 24.
Next, as shown in FIG. 1I, various layers of material that will constitute a replacement gate structure 30 are formed in the gate cavity 24. The materials used for the replacement gate structures 30 for NMOS and PMOS devices are typically different. For example, the replacement gate structure 30 for an NMOS device may be comprised of a high-k gate insulation layer 30A, such as hafnium oxide, having a thickness of approximately 2 nm, a first metal layer 30B (e.g., a layer of titanium nitride with a thickness of about 1-2 nm), a second metal layer 30C—a so-called work function adjusting metal layer for the NMOS device—(e.g., a layer of titanium-aluminum or titanium-aluminum-carbon with a thickness of about 5 nm), a third metal layer 30D (e.g., a layer of titanium nitride with a thickness of about 1-2 nm) and a bulk metal layer 30E, such as aluminum or tungsten.
FIG. 1J depicts the device 10 after several process operations were performed. First, one or more CMP processes were performed to remove excess portions of the gate insulation layer 30A, the first metal layer 30B, the second metal layer 30C, the third metal layer 30D and the bulk metal layer 30E positioned outside of the gate cavity 24 to thereby define the replacement gate structure 30 for an illustrative NMOS device. Then, one or more recess etching processes were performed to remove upper portions of the various materials within the cavity 24 so as to form a recess within the gate cavity 24. Then, a gate cap layer 32 was formed in the recess above the recessed gate materials. The gate cap layer 32 is typically comprised of silicon nitride and it may be formed by depositing a layer of gate cap material so as to over-fill the recess formed in the gate cavity and, thereafter, performing a CMP process to remove excess portions of the gate cap material layer positioned above the surface of the layer of insulating material 23.
As mentioned above, FIGS. 1B-1J depict an idealized situation where a replacement gate structure 30 is formed on a FinFET device. In practice, the portions of the fin C after formation of the sacrificial gate structure 40, i.e., before the formation of the spacers 20, is subjected to several process operations, such as ion implantation processes, cleaning processes, processes performed to remove masking layers, etc. As a result of the process operations, the physical size of the fin C beyond the channel region 17 of the device 10 is decreased in both height and width as compared to the portion of the fin C in the channel region of the device 10, i.e., the portions covered by the sacrificial gate structure 40. For example, by being exposed to multiple ion implantation processes, the fin material tends to amorphize to at least some degree, thereby making it more subject to removal when the amophized portions are exposed to later cleaning process operations.
FIG. 1K is a cross-sectional view taken through a fin C, while FIG. 1L is a plan view of a single fin C with the location of the replacement gate structure 30 and the spacers 20 indicated by dashed lines. As shown in FIG. 1K, the portions of the fin C that were not covered by the original sacrificial gate structure 40 are shorter than the portion of the fin C in the channel region, as indicated by the dimension 33. The dimension 33 may be about 3-5 nm in some applications. Similarly, as shown in FIG. 1L, the portions of the fin C that were not covered by the original sacrificial gate structure 40 have a width 35 that is less than the width 37 of the portion of the fin C in the channel region 17. In some cases, the loss of material of the fin structure in the areas outside of the channel region 17 may be as much as about 40 percent of the starting width of the fin C. This situation leads to an undesirable and significant increase in resistance of the device 10, which may result in reduced operational performance and/or power consumption by the device 10.
The present disclosure is directed to various methods of forming a replacement gate structure on a semiconductor device that may avoid, or at least reduce, the effects of one or more of the problems identified above.